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may 2007 rev 1 1/30 AN2503 application note pdp power devices introduction this application note discusses how to select optimal power devices and control circuitry for alternating plasma display panel applications , concentrating on power circuits used to sustain plasma discharge on the panel. plasma display panels (pdp) are emerging as the leading candidate for large area wall- hanging color tvs and hdtvs [ 1. ]. its large screen, wide viewing angle, and thinness have given it the edge over conventional displays. scan, energy recovery (erc) and sustain (discharge) circuits are important blocks that fulfill important energy saving requirements. www.st.com
contents AN2503 2/30 contents 1 pdp module structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pdp basic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pdp cell structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 panel memory characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 pdp driving sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 pdp sustain circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 sustain circuit operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.1 positive pulse of vyx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.2 positive discharge and clamping phase . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.3 vyx back to zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.4 clamping to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 symmetrical y - x phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 reset phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 pdp power devices characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 power devices from st . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.1 measurement set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.2 energy recovery section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1.3 discharge section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1.4 path section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1.5 set - reset section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 driving section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3 gate driver devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3.1 totem pole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4 input buffer section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 bill of material and schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AN2503 list of figures 3/30 list of figures figure 1. pdp module structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. cell structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. memory effect - no charges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. memory effect - address phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. memory effect - wall charges deposit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 6. memory effect - discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 7. memory effect - wall charges deposit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 8. memory effect - discharge with reverse polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 9. subfield structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 10. subfield structure ? expression of gray level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 11. sustain circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 12. circuit scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 13. circuit scheme ? positive pulse of v yx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 14. equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 15. circuit scheme ? positive discharge and clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 16. circuit scheme ? v yx back to zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 17. circuit scheme ? clamping to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 18. circuit scheme ? negative pulse of v yx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 19. circuit scheme ? negative discharge and clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 20. circuit scheme ? v yx back to zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 21. circuit scheme ? clamping to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 22. circuit scheme ? set and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 23. inductor current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 24. gate driver topology with l6385 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 25. gate driver topology ? l6388 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 26. sts01dtp06 totem pole. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 27. board schematic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 28. board schematic 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
pdp module structure AN2503 4/30 1 pdp module structure power supply, address buffer, logic and scan buffer boards are the fundamental blocks of a pdp. in particular, the energy recovery and sustain function are performed by the y and x drive boards. power mosfets, igbts, diodes and drivers are key products for erc and sustain both in x and in y drive boards. these products are also used for the path, set-reset function in the y drive board only. path switches are mandatory to isolate erc and sustain switches from the negative voltage applied to the display during the scan phase, while, set and reset switches determine id entical initial condition of the plasma cells before each address cycle. figure 1. pdp module structure st's extensive portfolio covers the whole solution for an energy recovery circuit (erc), sustain circuit, path circuit, and set-reset circuit, both from a power device and ic driver perspective. the st solution takes into account all fundamental requirements like cost, component count, reliability and power consumption. reduced power losses and higher switching frequency are the main benefits of st's advanced technology.
AN2503 pdp basic 5/30 2 pdp basic basic knowledge on plasma display panel encompasses manufacturing issues in cell structure, physics principle in the memory effect, and display algorithms needed to create a range of colors. 2.1 pdp cell structure figure 2 shows the structure of a plasma display glass panel, [ 2. ]. figure 2. cell structure an ac pdp display is composed of front and rear glass substrates sandwiched together and then sealed. the air is vacuumed out and a mixture of inert gases (ne and xe) is injected between the glass substrates. the separation between the two opposing substrates is about 100um and the spac e between them is fille d with a gas mixture of ne and xe. the front glass substrate has a first electrode (x elec trode) and a second electrode (y electrode) which operate as sustain electrodes. the x and y electrodes are coated with bus electrodes, dielectric layer, and mgo layer in sequence. the mgo protects the dielectric from plasma damage and also aids the plasma in sustaining a discharge through secondary electron emission from its surface. in additi on, equivalent capacitor exists between the x and y electrodes. on the surface of the rear gl ass substrate, as opposed to the front glass substrate, a third electrode operating as an address electrode (a electrode) is formed to be orthogonal to the x and y electrodes. electrically, the entire assembly can now be considered as a three-electrode capacitor. a cross point is formed where the x, y and a electrodes meet. three adjacent red, blue and green cross points form a color picture element (pixel) of the panel. in operation, an ac voltage suffi ciently high will ionize the gas to create the plasma. then, the ultraviolet light from the plasma excites the phosphor to create the color image. each pixel can be independently controlled and can assume different color gradations. the number of pixels available determines the resolution of the glass panel vertically and horizontally.
pdp basic AN2503 6/30 2.2 panel memory characteristic the ac pdps provide inherent memory characteristics [ 3. ], [ 4. ], as explained in the following figures. in general, the ac sustain square pulse voltage (v xy ), whose voltage vs is smaller than the gas breakdown voltage vbd, cannot initiate a discharge, as shown in figure 3 . figure 3. memory effect - no charges if data pulses vd are applied to the address electrodes, while scan pulses -vy are sequentially applied to each y electrode, the voltage (vd + vy) is higher than vbd and a weak discharge ignites, as shown in figure 4 . figure 4. memory effect - address phase charges, called wall charges (or wall voltage vw), deposit on the dielectric layer and reduce the effective voltage across the gap. then, the discharge ceases after a short time, as shown in figure 5 . figure 5. memory effect - wall charges deposit 3 address = vs/2 x = vs y = gnd 3 address = vd x = vk y = -vy address = vd x = vk y = -vy
AN2503 pdp basic 7/30 when the polarity of the sustain pulse is reversed, the potential difference across the gap becomes larger than vbd by an amount determined by the wall charges, and a new large discharge of different polarity occurs, as shown in figure 6 . figure 6. memory effect - discharge the build - up of wall charges again terminates the discharge, as shown in figure 7 . figure 7. memory effect - wall charges deposit the next discharge starts as the polarity of the sustain pulse is reversed, as shown in figure 8 . figure 8. memory effect - discharge with reverse polarity once the discharge is initiated, it continues as long as the sustain pulse is applied. due to this memory characteristic of ac pdps, lower sustain voltage (< vbd) pulses can maintain the ac pdps to light. in other words, the process of panel image displaying depends on a former process of panel addressing. in fact, during the address phase a small amount of charges (wall charges) deposit on the selected electrodes without any visible light emission. this reduces the address = vs/2 x = gnd y = vs 3 address = vs/2 x = gnd y = vs address = vs/2 x = vs y = gnd
pdp basic AN2503 8/30 threshold voltage for discharge, and consequently, during sustain phase only selected cells ignite and emit light. 2.3 pdp driving sequence the most common method of displaying one picture field is using the address display- separation method (asd). all x electrodes are bused together and connected to a sustain driver, while the y electrodes are connected to sustain driver thro ugh several scan ics. one tv field is divided into 10 subfields (sfs) in a 10-bit codification case, and each consists of a reset period, an address period, and a display period ( figure 9 ). on every subfield, each cell is addressed, sustained and erased. figure 9. subfield structure during the reset period a slow ramping positive voltage up to 400 v followed by slow ramping negative voltage down to -150 v is applied across the x and y electrodes to put out ionization and to set an identical initial condition for all the p anel cells. in the address period, the y electrodes receive scan pulses, along with data pulses on the address electrodes, in order to control wall charges in appropriate cells according to the image to be displayed. note that reset period and address period have the same duration in each subfield, only the number of sustain pulses varies among different subfields. during sustain period, selected cells are sustained in order to display the whole image on the panel. gray scales are expressed by using the binary-coded light-emission-period method. the display periods are filled with trains of constant width and constant period pulses, and their lengths are arranged according to the binary sequence, 1: 2: 4: 8: 16: 32: 64: 128: 256: 512. therefore, gray levels of 2 10 for each color (r, g, and b) can be expressed with an 10-bit sequence. this means that each color element has 1024 color possible graduations and each pixel ha s 1024 x 1024 x 1024 = 1 billion colors. figure 10 shows a simplified 8-bit system with 8 subfields. the subfields are weighted according to their binary values and a typical tv field is 1/50 of a second.
AN2503 pdp sustain circuit 9/30 figure 10. subfield structure ? expression of gray level 3 pdp sustain circuit in a plasma display panel, frequent dischar ges are made to occur by alternately charging each side of the panel to a critical voltage, allowing images to be displayed. this alternating voltage is called the sustain voltage, and the sustain circuit (or sustainer) is needed to provide it to the display [ 5. ]. if a pixel has been driven "on" during address period, the sustainer maintains the "on" state of that pixel by repeatedly discharging that pixel cell during the whole sustain period. if a pixel has been driven "off" by an address driver, the voltage across the cell is never high enough to cause a discharge, and the cell remains "off" during the sustain period. the sustain circuit must drive all panel pixels at once. this means that the capacitance as seen by the sustainer is typically very large. in a 42-inch panel with 852x480 pixels, the total capacitance of all the pixel cells, cp, could be as much as 80 nf. the key parameters in the sustainer study are: cp - panel equivalent capacitance vs - sustain voltage f - sustainer switching frequency f av - average sustainer switching frequency conventional sustain circuit (half bridge topology) drives the panel directly, and thus 1/2c p v s 2 f av is dissipated in the sustainer when th e panel is subsequently discharged to ground. in a complete sustain cycle, each side of the panel is charged to vs and subsequently discharged to ground. therefore, a total of 2cpvs 2 fav power is dissipated in a complete sustain cycle.
pdp sustain circuit AN2503 10/30 conventional sustain circuit (half bridge topology) drives the panel directly, and thus 1/2c p v s 2 f av is dissipated in the sustainer when the panel is subsequently discharged to ground. in a complete sustain cycle, each side of the panel is charged to vs and subsequently discharged to ground. therefore, a total of 2c p v s 2 f av is dissipated in a complete sustain cycle. figure 11. sustain circuit the power dissipation in the sustainer is then 2c p v s 2 f av , where f av is the average sustain cycle frequency. for cp=80 nf, vs =200 v, and f av = 100 khz, the power dissipation in the sustainer, resulting from driving the capacitance of the panel, could be as high as 640 w. if an inductor is placed in series with the panel, then cp can be charged and discharged through the inductor. this would ideally result in zero power dissipation since the inductor would store all of the energy otherwise lost in the output resistance of the sustainer and transfer it to or from cp. however, switching devices are needed to control the flow of energy to and from the inductor, as cp is charged and discharged, respectively, and this leads to power losses. the "on" resistance, output capacitance, and switching transition time are characteristics of these switching devices that can result in significant energy loss. the amount of energy that is actually lost due to these characteristics, and hence the efficiency, is determined largely by how well the circuit is designed to minimize these losses. in addition to charging and discharging cp, the sustainer must also supply the large gas discharge current for the plasma panel. this current, i, is proportional to the number of pixels that are "on" in the same tv frame. the resulting instantaneous power dissipation is i 2 r, where r is the output resistance of the sustainer. thus, the power dissipation due to the discharge current is proportional to i 2 , or the square of the number of pixels that are simultaneously "on". there are two ways to minimize this dissipation. the first is to reduce the output resistance of the sustainer by using very low resistance output drivers, and the second is to minimize the number of pixels that are "on" at any time. the switching power losses due to the panel capacitance during sustain period in ac pdp driving system can be minimized using a specific energy recovery circuit. the most common sustain/energy recovery circuit topology refers to weber topology ( figure 12 ).
AN2503 pdp sustain circuit 11/30 figure 12. circuit scheme weber topology provides a new sustainer circuit that recovers the energy otherwise lost in charging and discharging the panel capacitance, cp. the efficiency with which the sustainer recovers this energy is defined as the "recovery" efficiency. in particular, when cp is charged to v s and then discharged to zero, the energy that flows into and out of cp is e = c p v s 2 . the recovery efficiency is defined by: equation 1 where e lost is the energy lost in charging and discharging cp in the sustain circuit without energy recovery. it is worth noting that the recovery efficiency is not the same as the conventional power efficiency defined in terms of the power delivered to a load, since no power is delivered to the capacitor cp. it is simply charged and th en discharged. the recovery efficiency is a measure of the energy loss in the sustainer, and could reach a value higher than 90%. summarizing, the panel's pixels are connected in parallel and can be represented as an equivalent panel capacitor cp. a proper switching sequence, together with the energy recovery circuit, allows this circuit to produce an ac voltage required to illuminate, recover residual energy and reset the cells of the panel. referring to the schematic in figure 12 , power devices in the sustain circuit topology can be grouped into four circuit sub-functions: 1. energy recovery circuit (erc) which consists of t1, t2, t11, t12, d1, d2, d3, d4, d5, d6, d7, d8 2. sustain circuit (discharge circuit or su stainer) which consists of t3, t4, t9, t10 3. path circuit which consists of t5, t6 4. set and reset circuit which consists of t7, t8 vs vs vs vset l7 t9 t10 t8 x-electrode y-electrode t12 t11 -vreset cp cs1 cs2 l1 d7 d8 d6 d5 t7 d1 vs t3 t2 t1 t4 t6 t5 d2 d4 d3 eff 100 c p v s 2 e lost ? c p v s 2 ----------------------------------------- 100 1 e lost c p v s 2 ----------------- - ? ?? ?? ?? ? = ? =
pdp sustain circuit AN2503 12/30 3.1 sustain circuit operations sustain circuit operations describe the way to generate a square waveform on the panel capacitor. this section describes how to charge and discharge the panel capacitor in order to perform the sustain phase. 3.1.1 positive pulse of v yx after the reset period, we can suppose that all cells on the panel have been already addressed during the address period. this means that the cells to be displayed have accumulated enough wall charge to be ignited, due to cell memory effect. we can assume also that cs1 and cs2 have already their steady state voltage value, this means they have initial voltage of v s /2 from previous sustain cycles. in order to produce a positive voltage across the panel (v yx positive), t1, t5, t6 and t10 are turned on and d1 is forward biased. cs1 charges and raises the voltage across the panel capacitor cp in a resonant way. this step is a part of the energy recovery phase since it recovers the energy stored in the capacitor cs1 from previous sustain cycles back to the panel. figure 13. circuit scheme ? positive pulse of v yx the equivalent circuit during the lc resonant period of the energy recovery circuit is: figure 14. equivalent circuit in figure 14 , r represents the parasitic resistance in cluding on-resistances of switches and v on represents the diode forward drop. based on this figure, the panel voltage v yx can be obtained as follows: equation 2 vs vs vs vset l7 t9 t10 t8 x-electrode y-electrode t12 t11 -vreset cp cs1 cs2 l1 d7 d8 d6 d5 t7 d1 vs t3 t2 t1 t4 t6 t5 d2 d4 d3 v yx v s 2 ------ v on ? ?? ?? 1e t -- - ? t cos r l ------ t sin + ?? ?? ? =
AN2503 pdp sustain circuit 13/30 where if (2l/r) 2 and ( r/l) can be ignored, the equation ( equation 2 ) can be simply re-written as: equation 3 where if ? = then the peak value is: equation 4 equation 4 states that an increase of the parasitic resistance causes the recovery efficiency to be degraded. naturally, it is necessary to reduce the parasitic resistance by designing the circuit board optimally as well as choosing switching devices with small on-resistance and low on-drop voltage to minimize the hard-switching stress and improve the recovery performance. on the other hand, reduction of the inductor value produces similar results and, thus, using a too small value of l is not desirable with respect to driving loss. 3.1.2 positive discharge and clamping phase figure 15 shows both panel discharge and the camping current paths. in the first phase the ionized gas could be represented as a non linea r resistor and the peak current during this period is higher than that during energy recovery. the worst condition is represented when all cells in the panel must be ignited (full white screen condit ion), and in this case the discharge current could be higher than 120 a for a standard definition (sd) 42-inch pdp set. further increase in the current value is expe cted in hd pdp as the number of pixels increases. figure 15. circuit scheme ? positive discharge and clamping r l ------- ?? ?? = 1 lcp ----------- ?? ?? r 2l ------ - ?? ?? 2 ? = and v yx v s 2 ------ v on ? ?? ?? 1e t -- - cos ? = t 1 lcp ----------- = ? v yx pk , v s 2 ------ v on ? ?? ?? 1e r 2 ------- c p l ------ ? ? = vs vs vs vset l7 t9 t10 t8 x-electrode y-electrode t12 t11 -vreset cp cs1 cs2 l1 d7 d8 d6 d5 t7 d1 vs t3 t2 t1 t4 t6 t5 d2 d4 d3
pdp sustain circuit AN2503 14/30 the discharge current has also a sinusoidal profile, and is conducted by t3, t6, t5, cp, and t10. once the panel is charged to vs and visi ble light is emitted, current stops flowing and the gas inside the glass stops ionizing. (note that the use of igbts in the discharge section requires extra care; indeed power devices requires freewheeling diodes to carry reverse current due to the tank circuit formed between the panel capacitor cp, l1 and the bus capacitance). at this time d1 is reverse biased and its reverse current charges the inductance l1. the energy stored in the inductance is removed through the clamping current, and the clamping current path is carried out by t3, d3, and d2. in this phase the reverse current of d1 is a key parameter in power loss reduction. in fact, a lower clamping current means lower conduction losses in t3, d2 and d3. depending on the to pology used, and in particular the clamping diode's position, the time spent to evacuate the energy stored in the inductance can vary significantly. 3.1.3 v yx back to zero the next phase consists of bringing back to zero the panel capacitor voltage and reverse the polarity of the voltage across y-x electrodes. in order to efficiently decrease the voltage on the panel capacitor, the energy stored in cp could be recovered back in the recovery capacitor cs1.this can be done by turning on t2, t6, t5, and t10. the current path is shown in figure 16 . this current stops flowing when the voltage across the panel capacitance v yx and cs1 reach the same value (vs/2). the profile of this current is half sinusoidal and its direction is from the panel cp back to cs1. figure 16. circuit scheme ? v yx back to zero 3.1.4 clamping to ground in order to bring completely to zero the panel capacitance, t10, t5, t6, and t4 are turned on, creating a current path across the panel through the equivalent resistances of power devices and parasitic elements of the circuit. vs vs vs vset l7 t9 t10 t8 x-electrode y-electrode t12 t11 -vreset cp cs1 cs2 l1 d7 d8 d6 d5 t7 d1 vs t3 t2 t1 t4 t6 t5 d2 d4 d3
AN2503 pdp sustain circuit 15/30 figure 17. circuit scheme ? clamping to ground 3.2 symmetrical y - x phase a similar switching sequence is applied in order to reverse the polarity across y-x electrodes (x electrode more positive than y electrode) in particular, this can be briefly described as: a) energy recovery, path and discharge switches, t12, t5, t6, and t4 are turned on, and the current flows from cs2 to cp. figure 18. circuit scheme ? negative pulse of v yx b) discharge and clamp phases: t9, t4, t5, t6 are turned on and the current flows from vs to cp and through t9, l7, d7, d8. figure 19. circuit scheme ? negative discharge and clamping vs vs vs vset l7 t9 t10 t8 x-electrode y-electrode t12 t11 -vreset cp cs1 cs2 l1 d7 d8 d6 d5 t7 d1 vs t3 t2 t1 t4 t6 t5 d2 d4 d3 vs vs vs vset l7 t9 t10 t8 x-electrode y-electrode t12 t11 -vreset cp cs1 cs2 l1 d7 d8 d6 d5 t7 d1 vs t3 t2 t1 t4 t6 t5 d2 d4 d3 vs vs vs vset l7 t9 t10 t8 x-electrode y-electrode t12 t11 -vreset cp cs1 cs2 l1 d7 d8 d6 d5 t7 d1 vs t3 t2 t1 t4 t6 t5 d2 d4 d3
pdp sustain circuit AN2503 16/30 c) energy recovery phase: t4, t5, t6, and t11 are turned on, and the current flows from cp to cs2. figure 20. circuit scheme ? v yx back to zero d) zero voltage clamp, t4, t5, t6, t10 are turned on. figure 21. circuit scheme ? clamping to ground it can be noted that during sustain phase, path switches t5 and t6 are always turned on, and they see both energy recovery current and discharge current which explains the need for low voltage drop devices. 3.3 reset phase at the end of each subfield, the cells are reset applying a positive ramp voltage followed by a negative one. during positive reset, t10, t5, t7 are turned on. during negative reset t10 and t8 are turned on. vs vs vs vset l7 t9 t10 t8 x-electrode y-electrode t12 t11 -vreset cp c s1 cs 2 l1 d7 d8 d6 d5 t7 d1 vs t3 t2 t1 t4 t6 t5 d2 d4 d3 v v v vse l t t1 t x-electrode y - e l e c t1 t1 c cs cs l d d d d t d v t t t t d d
AN2503 pdp power devices characteristics 17/30 figure 22. circuit scheme ? set and reset 4 pdp power devices characteristics a clear idea of circuit operation will help us to highlight the main features of the devices involved. in particular the analysis can be sp lit in power devices analysis and driving devices analysis, in order to address specific characteristics of each device. 4.1 power devices from st power devices in pdp have common characteristics that range from high peak current capability and low forward voltage drop to fast turn-on capab ility. the curren t both in the energy recovery circuit (erc) and in the disch arge circuit (dc) follows a half sinusoidal pattern. erc and dc could be simply classified as soft switching converters. in fact, the circuit can be considered as a series resonant lcr circuit, so the current at turn-on is zero (zero current switching) and the voltage at turn-off is zero (zero voltage switching). since a mosfet has an intrinsic body diode across it, a mosfet does not require an anti- parallel diode when selected as power devices on the discharge circuit, while an igbt needs a specific freewheeling diode. for er circuit, the power switch does not require an anti-parallel diode since reverse current is blocked by the diodes in series with the devices (d1, d3, d5 and d7), thus mosfet or igbt can be used as power devices on the er circuit. diodes d2, d4, d6 and d8 provide additional protection clamping the voltage on the inductors avoiding damage to devices on the er circuit. path circuit has to carry both er and discharge currents, thus it is required to have very low voltage drop. it can be noted that during er and discharge cycles, the pass circuit remains on. the path circuit switches on and off only during reset period which happens at the end of each subfield, which means that the maximum frequency is in the range of 1 khz. the path circuit is a bidirectional circuit, so a mo sfet, that can carry current in both directions, could be used for this circuit. st has a broad range of products covering the power section ranging from mosfet and igbt to dedicated diodes. vs vs vs vset l7 t9 t10 t8 x-electrode y-electrode t12 t11 -vres et cp cs1 cs2 l1 d7 d8 d6 d5 t7 d1 vs t3 t2 t1 t4 t6 t5 d2 d4 d3
pdp power devices characteristics AN2503 18/30 4.1.1 measurement set-up power losses and thermal analysis measurements were performed based on an average switching frequency. in fact, switching performances have to be related to the maximum frequency in the system, usually 250 khz, whereas power losses and thermal management have to be related to an average frequency. the average switching frequency takes into account the fact that during a picture time, the power devices do not switch at the maximum frequency for the whole time, but only during the sustain phases. the sustain duration, and consequently the number of sustain pulses, increases starting from subfield 1 to subfield 10. average frequency can be calculated starting from sustain duty ratio. note: sustain duty = picture time - reset period x sf - n x sf x scan speed [ s / line] picture time = 16.67 ms reset period = 250 sec sf = number of sustain pulses n = number of lines the sustain duty ratio is carried out for a 10 subfield case in both single scan and dual scan operations, varying the scan speed duration (time needed to scan a single line in the display), for vga (480 lines), xg a (768 lines) and hd (1080 lines). according to the following formula, f av =f switching x sustainduty for a vga display sustainduty = 0.27 0.56 f av = 68 140 khz this means that power devices in erc and discharge circuit need to be designed for an average frequency of 140 khz (maximum) in terms of power losses and thermal management. clearly peak current and peak voltage rating do not change when we perform this averaged analysis. table 1. 10 subfield / single scan scan speed vga 480 xga 768 hd 1080 3 sec - - - 2.5 sec 0.130 - - 2 sec 0.274 - - 1.5 sec 0.418 0.159 - 1 sec 0.562 0.389 0.202 table 2. 10 subfield / dual scan scan speed vga 480 xga 768 hd 1080 3 sec 0.418 0.158 - 2.5 sec 0.490 0.274 0.040 2 sec 0.562 0.389 0.202 1.5 sec 0.634 0.504 0.364 1 sec 0.706 0.620 0.526
AN2503 pdp power devices characteristics 19/30 typical voltage requirements for a pdp are: sustain voltage vs = 200 v set voltage vset= 400 v reset voltage vreset= -150 v 4.1.2 energy recovery section for energy recovery circuit, the maximum voltage stress is vs/2 100 v, and the current stress depends on the device. the clamping di odes have to withstand a current lower than 10 a, whilst the erc switches and the erc diodes have to be able to handle a resonant half-sinusoidal current up to 100 a peak. the typical current waveform in the energy recovery circuit is shown in figure 23 . the key parameters of the derc diode for the energy recovery circuit have been optimized in order to decrease power losses. figure 23. inductor current for er circuit new devices with low voltage drop and very fast turn on have been developed. energy recovery diodes stth60p03, stth40p03 energy recovery diodes (d1, d3, d5, and d7) have been tailored on this application optimizing key parameters to reduce power losses [ 6. ], [ 7. ]. they have the ability to handle large repetitive peak current (irp), in conjunction with a lower reverse current (i rm ) and peak forward voltage (v fp ). table 3. stth60p03 features symbol parameter test conditions min. typ max. unit i rm reverse recovery current t j = 100c i f = 60 a v r = 100 v di f /dt = 200 a/s 67.5a s factor softness factor 0.5 v fp peak forward voltage t j = 25c i f = 60 a di f /dt = 400 a/s 2.5 3.5 v erc current t1 clamping current t3 d2 d3
pdp power devices characteristics AN2503 20/30 clamping diodes stth2003, stth1003 diodes d2, d4, d6, and d8 provide additional protection to clamp the voltage on the inductors [8], [9]. overvoltage is due to er diodes reverse current that store energy in the inductors. the fact that reverse current i rm of erc diodes stores energy in the inductors (and can cause overvoltage if we do not use clamping diodes d2, d4, d6, and d8), demonstrates that the i rm in erc diodes is a key parameter to take into account. in fact, i rm causes power losses both in clamping diodes and discharge switches. energy recovery mosfet st75n20 t1, t2, t11, and t12 are the power switches used in the energy recovery circuit. due to the reactive nature of the load, the voltage across the power switch falls rapidly followed by a rapid rise in the current. this explains why a fast turn-on is needed, and low conduction losses (low drop) can be achieved only reducing the r dson . the stw75n20 power mosfet in proprietary stripfet tm technology, thanks to its low r dson and low gate charge is perfectly tailored for the application [ 9. ]. 4.1.3 discharge section when the panel discharges, a sinusoidal shaped current will go th rough the discharge switches. the current could reach a peak value higher than 120 a in worst condition (full white screen), thus low r dson and fast turn-on are required. maximum voltage stress for discharge circuit is vs = 200 v discharge mosfet stw52nk25z the stw52nk25z power mosfet in property supermesh tm technology, and due to its low r dson and low gate charge is perfectly tailored on the application [ 10. ]. 4.1.4 path section for path circuit, mosfet is the preferred device since this circuit is required to conduct current in both directions. the switching frequency is low, and the rms current through this table 4. clamping diodes features p/n i f [a] v rrm [v] t rr [ns] tj[c] v f [v] package stth1003 10 300 13 175 0.9 dpak, to-220fp, d 2 pa k stth2003 2x10 300 35 175 1 dpak, to-220fp, d 2 pak, to220 table 5. erc mosfet features p/n v dss [v] r dson [ ? ] i d /i dmax [a] p [w] package st75n20 200 0.028 75/300 300 to-247, to-220, d 2 pa k table 6. sustain mosfet features p/n v dss [v] r dson [ ? ] i d /i dmax [a] p [w] package p/n stw52nk25z 250 0.033 52/208 300 to-247 stw52nk25z stw54nk30z 300 0.060 54/200 300 to-247 stw54nk30z
AN2503 pdp power devices characteristics 21/30 circuit is very large since it has to con duct both er and discharge currents. both stripfet tm and supermesh tm power mosfets technologies from st are ideal for this application since they allow the die to have very high current density and therefore reduce the number of paralleled devices required to maintain very low voltage drop [ 9. ], [ 10. ], [ 11. ], [ 12. ]. for path switch in t6 position, the maximum voltage stress is (vs + vset) / 2 300 v, while for path switch in t5 position, the maximum voltage stress is (vset + |vreset|) / 2 275 v. 4.1.5 set - reset section the set and reset circuit applies asymmetrical ac voltage across the panel in order to evacuate any remaining surface charge from the cells. this is usually done at the end of each subfield (or the beginning of the next subfield), and the power devices on this circuit operate in the linear mode. this means that the voltage drop is very large but the current through the device is relatively low. due to the requirement of asymmetrical set and reset voltages, power switches in the set and reset circuits have to block up to 600 v. typical voltage value for set function is 400 v and for reset function is -150 v. this means that the maximum voltage stress for set circuit t9 is (vs + vset) = 600 v while the maximum voltage stress for reset circuit t10 is vset + |vreset| = 550 v. st offers two families of products for this se ction both appreciable for their ruggedness for linear applications. example device is stgp10nb60s in the igbt planar technology [ 13. ]: further examples of devices are supermeshtm devices as follows [ 14. ], [ 15. ]. table 7. path mosfet features p/n v dss [v] r dson [ ? ] i d /i dmax [a] p [w] package st60nk30zd1 300 0.045 60/240 450 die or max247 stw52nk25z 250 0.033 52/208 300 to-247 st75n20 200 0.028 75/300 300 to-247, to-220, d 2 pa k st40n20 200 0.045 40/160 160 to-247 to-220 d 2 pak to220fp table 8. set ? reset igbt features p/n v ces [v] v ce(sat) [ ? ] i c [a] package stgp10nb60s 600 1.7 10 d 2 pa k table 9. set-reset mosfet features p/n v dss [v] r dson [ ? ] i d /i dmax [a] p [w] package st9nk70z 700 1 7.5/30 115 w to-220 d 2 pak to220fp st14nk60z 600 0.5 13.5/54 160 w to-220 d 2 pak to220fp
pdp power devices characteristics AN2503 22/30 4.2 driving section driving section devices range from gate driver devices to input buffer ones. gate driver function is carried out by a gate driver ic and a push pull amplifier. driving section can be split in: gate driver section: l6385 or l6388 push pull section: sts01dtp06 input buffer section 74vhct541 4.3 gate driver devices st offers the widest series among the high voltage half-bridge gate drivers (the l638x series), manufactured with bcd"off-line" technology. they are able to work in applications with with voltages to 600 v. in the l638x series the two selected drivers are the l6388 [ 16. ] and the l6385 [ 17. ], which can drive two power mosfets or igbts, one high- side and one low-side, in a half-bridge or different topology. l6388 is especially effective in applications where logic input must be compatible with 3.3 v logic. another key feature of the l6388 is that it provides effective anti-shoot-through circuitry which prevents two power mosfets or igbts from being turned on at the same time. this is achieved by introducing a 200 ns time interval, a "dead time" between the moment one of the components is turned off and the other is turned on. l6385 is able to drive asymmetrical half bridge, but its logic input is not comp atible with 3.3v logic. the main features of these hv gate drivers are: dv/dt immunity +- 50 v/nsec in full temperature range driver current capability: ? 400 ma source ? 650 ma sink switching time 50/30 nsec rise/fall with 1 nf load under voltage lock-out on lower and upper driving section internal bootstrap diode outputs in phase with inputs due to different characteristics, the topologies used in energy recovery circuit and sustain circuit depend on the driver used as shown in figure 24 and figure 25 .
AN2503 pdp power devices characteristics 23/30 figure 24. gate driver topology with l6385 figure 25. gate driver topology ? l6388 due to current value in bootstrap charge, the internal diode cannot be used, thus external diode smby01-400 [ 20. ] must be used. further details on l6585 and l6588 application can be found in [ 18. ] and [ 19. ]. 4.3.1 totem pole in order to match inherent power devices characteristics, (as high gate charge) with drivers current capability, tote m pole sts01dtp06 [ 21. ] in a push pull configuration is used in the application. the sts01dtp06 is housed in the smd dual island so-8 package and allows an optimized electronic solutions, by improving circuit efficiency, saving space and reducing component count on the board. the sts01dtp06 is a hybrid complementary npn and pnp bipolar transistor manufactured using the latest low voltage planar technology. extremely efficient performance is obtained by combining high pulse current, excellent gain and fast speed, vcc hin lin gnd 1 3 2 4 out hvg vboot 8 7 6 5 lvg vcc l638x vcc to plasma vs vs vs vs vcc hin lin gnd 1 3 2 4 out hvg vboot 8 7 6 5 lvg vcc l638x vcc vs/2 vs/2 pp pp pp pp pgy vcc hin lin gnd 1 3 2 4 out hvg vboot 8 7 6 5 lvg vcc l638x vcc to plasma vs vs vs vcc hin lin gnd 1 3 2 4 out hvg vboot 8 7 6 5 lvg vcc l638x vcc vs/2 pp pp pp pp
pdp power devices characteristics AN2503 24/30 resulting in low losses in hi gh frequency applications. the sts01dtp06 offers a 30 v npn and pnp combination supporting a continuous collector current of 3 a and the minimum gain of the two transistors is 100 at 1 a collector current. the transistor elements are fully independent so that higher asse mbly flexibility is guaranteed. concerning pdps, this means that the turn-on and the turn-off resistors could be different. figure 26. sts01dtp06 totem pole the sts01dtp06 main features are summarized in ta bl e 1 0 : 4.4 input buffer section the 74vhct541 is an advanced high-speed cmos octal bus buffer (3-state) fabricated with sub-micron silicon gate and double-layer metal wiring c2mos technology, available in tssop package [ 22. ]. in order to enhance pc board layout, the 74vhct541 offers a pin-out having inputs and outputs on opposite sides of the package. the device is characterized by high speed and low power dissipation. power down protection is provided on all inputs and 0 to 7 v can be accepted on inputs with no regard to the supply voltage. this device can be used to interface 5 v to 3 v. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. table 10. sts01dtp06 features part number v ceo [v] i c [a] p tot [w] h fe min vce(sat)@ max [v] i c [a] i b [ma] npn pnp sts01dtp06 30 3 1.6 100 0.7 2 100
AN2503 bill of material and schematics 25/30 5 bill of material and schematics ta bl e 1 1 gives the bom and the schematics of the demo board. table 11. bill of material item qty reference value & comment 1 5 c1,c4,c23,c26, c44 2.2 f 50 v 2 5 c2,c3,c24,c25,c45 100 nf 50 v 3 4 c5,c6, c20,c21 2.2 nf 400 v 4 4 c16,c17,c18,c19 3.3 f 250 v 5 1 c22 104 k 250 v 6 8 c27,c28,c29,c30,c48,c49,c50,c51 100 f 250 v 7 2 c35,c36 100 f 25 v 8 7 c37,c38,c39,c40,c41,c42,c43 100 pf 10 v 9 2 c46,c47 x1 capacitor modeling the panel 10 4 d1,d7 smby01-400 11 2 d2,d10 stth60p03sw 12 3 d3,d8 stth2003cg 13 3 d14 diode z.16 v 14 1 f1 5a 250 v fuse 15 2 f2,f3 1a 125 v 16 1 j1 header 9 17 2 j4,j13 connector 2 pins 18 1 j7 gnd-star connector 19 1 j18 header 30 20 2 l5,l6 500 nh inductor 21 2 l12,l14 10 h inductor 22 2 r2,r19 2,2 ? smd resistor 23 8 r7,r8,r9,r10,r17,r18,r21,r22 3.9 ? smd resistor 24 2 r1, r20 36 ? smd resistor 25 5 r35,r36,r37,r38,r39 200 ? smd resistor 26 4 r50, r51 100 k ? smd resistor 27 6 r3, r4, r23, r24, r25 1 ? smd resistor 28 6 r26,r40,r41,r42,r43,r44 100 ? smd resistor 29 3 r27 10 k ? smd resistor 30 2 u1,u5 l 6385 31 4 u2,u3,u6,u7 sts01dtp06
bill of material and schematics AN2503 26/30 figure 27. board schematic 1 32 1 u8 74vhct541 33 4 u11,u12,u14, u16 stw52nk25z 34 2 u13,u15 stw75n20 35 3 j15, j16, j17 connector 17 pins table 11. bill of material (continued) item qty reference value & comment v sustain v sustain vcc c26 22uf-50v u16 stw52nk25z u6 sts01dtp06 1 2 3 4 5 6 7 8 e1 b1 e2 b2 c2 c2 c1 c1 c25 100nf c47 x1 c21 2.2nf c19 3.3uf 250v c16 3.3uf 250v r27 10k d14 diode z.16v r17 3.9 r51 100k u7 sts01dtp06 1 2 3 4 5 6 7 8 e1 b1 e2 b2 c2 c2 c1 c1 u5 l 6385 1 2 3 4 5 6 7 8 lin hin vcc gnd lgv vout hgv vboot u15 stw75n20 c23 22uf-50v c17 3.3uf 250v c31 33pf r19 2.2 d10 stth60p03sw a1 k a2 r20 36 r24 1 c22 104k 250v c18 3.3uf 250v r21 3.9 c24 100nf r26 100 u14 stw52nk25z d8 stth2003cg r50 100k c20 2.2nf r25 1k r231 r22 3.9 d7 smbyt01-400 c46 x1 r18 3.9 u11 stw52nk52z r7 3.9 r4 1 r3 1. u13 stw75n20 c4 22uf-50v d1 smbyt01-400 r9 3.9 c3 100nf r2 2.2 r8 3.9 c6 2.2nf 400v j4 con2 1 2 d2 stth60p03sw 1 2 3 a1 k a2 c2 100nf c1 22uf-50v u3 sts01dtp06 1 2 3 4 5 6 7 8 e1 b1 e2 b2 c2 c2 c1 c1 d3 stth2003cg u2 sts01dtp06 1 2 3 4 5 6 7 8 e1 b1 e2 b2 c2 c2 c1 c1 l6 500nh c5 2.2nf 400v r10 3.9 u12 stw52nk25z l5 500nh u1 l 6385 1 2 3 4 5 6 7 8 lin hin vcc gnd lgv vout hgv vboot r1 36 lin u4005 v sustain/2 v sustain hin u4005 display vcc res ind vcc display res ind v sustain/2 hin u4004 lin-u4004 t11 t10 t10 t12 t9 t9
AN2503 bill of material and schematics 27/30 figure 28. board schematic 2 c35 100uf 25v c36 100uf 25v c37 100pf c38 100pf c39 100pf c40 100pf c41 100pf c42 100pf c43 100pf l12 10uh l14 inductor f1 fuserid f2 fuserid f3 fuserid j15 conn socket 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 c48 j18 header 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 c49 j16 conn socket 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 c50 j1 header 9 1 2 3 4 5 6 7 8 9 j17 conn socket 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 j7 gnd-star 1 2 c51 j13 enable 1 2 u8 st74v hct541 1 2 3 4 5 6 7 8 9 10 19 20 11 12 14 13 15 16 17 18 1 2 3 4 5 6 7 8 9 10 19 20 11 12 14 13 15 16 17 18 r30 1k r31 1k r32 1k r33 1k r34 1k r35 200 r36 200 r37 200 r38 200 r39 200 c44 22uf25v r40 100 r41 100 r42 100 r43 100 r44 100 c27 100uf250v c28 c29 c30 c45 100nf xr xs xf xg xb lin-u4004 hin u4004 hin u4008 hin u4005 lin u4005 vcc vdd v sustain vb vdd xg xr xb xf xs display xg xr xs xb xf
conclusions AN2503 28/30 6 conclusions st offers its customers a complete product portfolio covering the whole pdp. st's system approach helps customers design effective energy recover (erc) and sustain circuits, improving their time-to-market. pdp power consumption is greatly reduced using st's dedicated products. 7 references 1. "plasma displays," ieee trans. plasma sci., vol. 19, pp. 1032-1047, dec. 1991. 2. "cell structure and driving method of a 25 -in (64 cm) diagonal hi gh-resolution color ac plasma display," in proc. symp. society for information display, vol. 29, 1998, pp. 279- 282. 3. "charge spread ing and its effect on ac plasma p anel operating margins," ieee trans. electron devices, vol. ed-24, pp. 870-872, july 1997. 4. "measurement of wall charges in a surface discharge ac-pdp," in proc. int. display workshops, 1997, pp. 527-530. 5. " power efficient sustain drivers and address drivers for plasma panel," u.s. patent 4 866 349, sept. 1989 and u.s. patent 5 081 400, jan. 1992. 6. stth60p03sw datasheet 7. stth40p03sw datasheet 8. stth2003cg datasheet 9. stw75n20 datasheet 10. stw52nk25z datasheet 11. stp40n20 datasheet 12. st60nk30zd1 datasheet 13. stgp10nb60s datasheet 14. stp9nk70z datasheet 15. stb14nk60z datasheet 16. l 6388 datasheet 17. l 6385 datasheet 18. an994 - l6384, l6385, l6386, l6387 application guide 19. an1299 - l6384, l6385, l6386, l6387: tips & tricks 20. smby01-400 datasheet 21. sts01dtp06 datasheet 22. 74vhct541 datasheet
AN2503 revision history 29/30 8 revision history table 12. revision history date revision changes 02-may-2007 1 first issue
AN2503 30/30 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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